1. Field of the Invention
This invention relates generally to analog-to-digital converters and, more specifically, to apparatus and methods using delta-sigma analog-to-digital converters.
2. Description of the Related Art
Recently, the telecommunications community has considered data receivers in which analog-to-digital (AD) conversion happens very close to the receiving antenna. Performing AD conversion close to the receiving antenna significantly reduces the amount of signal processing, e.g., filtering and demodulation, performed in the analog domain. Instead, when AD conversion occurs near the receiving antenna, signal processing is performed on the digital signals produced by AD conversion. The displacement of signal processing to the digital domain is desirable, because digital devices typically have lower temperature sensitivities, more linear behavior, and higher component tolerances than their analog counterparts.
One type of AD converter is known as a delta-sigma AD converter (Δ-Σ ADC). Referring to FIG. 1, an exemplary Δ-Σ ADC 2 includes a clocked quantizer 4, a loop filter 5, and a feedback loop 6 with a digital-analog (DA) converter 7. The quantizer 4 performs a sampling operation that produces the analog-to-digital conversion. The feedback loop 6 produces analog signals with values responsive to the values of the digital output signals from the quantizer 4 and feeds the analog signals back. The fed back analog signals are sequentially combined with an analog input signal to form the analog signal that the loop filter 5 will process. For example, an adder 8 may add the fed back analog signals to analog input signals, and/or one or more intermediate taps 9 into the loop filter 5 may combine the fed back analog signals with analog signals generated in the loop filter 5.
By feeding back signals responsive to the digital output signals, Δ-Σ ADCs reduce the contribution of quantization noise to selected frequency components of the digital output signal. For the selected frequency components, signal-to-noise ratios (SNR) are typically higher in Δ-Σ ADCs having higher oversampling ratios (OSRs) than in Δ-Σ ADCs having lower OSRs. Herein, the OSR is defined as the ratio of an AD converter's sampling frequency to the data bandwidth of the analog input signal being digitalized by the AD converter. In the selected frequency band, the value of the SNR is also typically higher in Δ-Σ ADCs with high-order loop filters than in Δ-Σ ADCs with low-order loop filters. Unfortunately, high-order loop filters also can cause unacceptable instabilities into the operation of a Δ-Σ ADC.
Some conventional Δ-Σ ADCs use fourth-order loop filters and quantizers with high sampling frequencies, e.g., sampling frequencies that are four times the center carrier frequency of the analog input signal.